The preferred embodiments relate to circuits with package on package (PoP) memory interfaces, as well as configurations including the PoP memory interface and coupled memory.
By way of background, FIG. 1 illustrates a cross-sectional side view of an integrated circuit PoP designated generally at 10. The configuration as shown in FIG. 1 is consistent with the prior art, but notably the preferred embodiments also are suitable for implementing in a same configuration, albeit with greater functionality and benefits as detailed later. By way of general introduction to both the prior art and the related packaging considerations of the preferred embodiments, therefore, PoP 10 has two or more integrated circuit packages 20 and 30 (also known as chips) stacked relative to one another, typically for saving space to serve application requirements where area or volume is constrained. For example, automobile applications in confined areas of a vehicle may call for PoP devices, as may other consumer devices, such as cell phones and cameras. In general, the overall dimensions of integrated circuit PoP, shown generally two dimensionally D1 by D2, but understood to include a third dimension D3 perpendicular to D1 and D2, typically occupy one cubic inch, or less.
Each device 20 and 30 includes at least one functional die 22 and 32, respectively, atop a respective substrate 24 and 34. The two (or more) stacked PoP devices 20 and 30 may serve comparable functions such as multiple memories, or in a mixed logic-memory stacking the devices may differ, such as having a System-On-A-Chip (SoC) processor as the lower device, with memory stacked on top of the SoC processor and providing electronic storage to the processor. Each functional die 22 and 32 is encapsulated in a respective cover 26 and 36. Each package 20 and 30 has a respective set of connectors, typically by way of a ball grid array (BGA) 28 and 38. BGA 28 allows electrical connections between packages 20 and 30, while BGA 38 allows connections between package 30 and additional lines, such as are typically on a printed circuit board (PCB). In any event, the stacked arrangement of the PoP configuration reduces the two-dimensional space needed as compared to arranging the two chips separately in a generally same two dimensional plane. Other PoP advantages include shorter track length in the connections between the stacked devices, thereby improving performance, such as increasing speed and noise resistance.
While PoP configurations are increasingly useful and provide benefits as described above, it has been observed in connection with the preferred embodiments that PoP configurations may provide limitations. Specifically, because of the confined volume created by PoP stacking, typically the number of pin connections between the stacked devices is limited, due to the layout of die on each stacked device and the stacked perimeter, as typically occupied by the BGA. One manner observed in which such pin limitations arises is the lack of support for data checking by memories manufactured for PoP applications. More particularly, as technology advances, there again arises a need for smaller devices where PoP might appear usable, but at the same time some environments and applications also are increasing the use of so-called “mission critical” data. For example, in contemporary automotive applications, data that formerly was not mission critical is evolving toward mission critical, as may be guided by manufacturer requirements or regulations, such as via Automotive Safety Integrity Level (ASIL). Consider the instance of video data for a vehicle backup camera; such data in some applications may not by itself be mission critical when used solely to depict an image to a vehicle operator, but as such data becomes used for vehicle control, such as controlling brakes, steering, or acceleration, the criticality of the data is considerably increased. Such mission critical data, by definition, requires assurances of greater if not absolute accuracy. In PCB layouts, some accuracy is sometimes achieved through the use of a single parity bit per byte (or other quantum) of data, or for greater accuracy, error code correction (ECC) bits are used, wherein multiple ECC bits are generated, typically by hashing a byte (or other quantum) of data. Either the parity bit or ECC bits are used to verify data that is simultaneously communicated with the parity/ECC, and in the instance of an error then correction of the error is facilitated. For PoP applications, however, memory manufacturers construct memories (e.g., low power double data rate memory—LPDDR2/3) with a limited number of pins, presumably due to the confined area of PoP technology. As a result, such memory does not support parity/ECC. Moreover, the prior art PoP memory interface also does not support parity/ECC, again presumably due to the space constraints of PoP stacking as well as the general availability of memory usable in PoP architectures.
Further with respect to the above, FIGS. 2a and 2b illustrate electrical block diagrams of the limitations in prior art PoP LPDDR2 memory and interfacing configurations. For example, FIG. 2a illustrates a 32-bit PoP external memory interface PEMIF1 which, consistent with the typical commercially available 32-bit PoP memory PMEM1 (e.g., SDRAM), provides only data pins D[31:0], but no additional error information. Similarly, FIG. 2b illustrates a 16-bit PoP external memory interface PEMIF2 which, consistent with the typical commercially available 16-bit PoP memory PMEM2, provides only data pins D[15:0] but no additional error information.
Given the preceding, the present inventors have identified potential improvements to the prior art, as are further detailed below.